(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of removing damage to I/O pads that have been contacted by test probes, thereby avoiding potential solder bump reliability problems.
(2) Description of the Prior Art
The creation of monolithic integrated circuits requires the creation of numerous interacting electrical device elements, which are typically created in or on the surface of a semiconductor substrate. Among these device elements are transistors, diodes, bipolar transistors, CMOS Field Effect Transistors of either N or P channel type and the like. After semiconductor devices and device elements have been created, these devices and device elements must be interconnected in order to form functional semiconductor devices. In addition, the interconnected devices and device elements are further connected to semiconductor substrates, printed circuit boards, flex circuits or a metallized or glass substrates or semiconductor device mounting supports.
In creating semiconductor devices, the technology of interconnecting devices and device features is a continuing challenge in the era of sub-micron devices. Bond pads are frequently used for this purpose, whereby continuous effort is dedicated to creating bond pads that are simple, reliable and inexpensive.
Bond pads are generally used to wire device elements and to provide exposed contact regions of the die. These contact regions are suitable for wiring the die to components that are external to the die. An example is where a bond wire is attached to a bond pad of a semiconductor die at one end and to a portion of a Printed Circuit Board at the other end of the wire. The art is constantly striving to achieve improvements in the creation of bond pads that simplify the manufacturing process while enhancing bond pad reliability.
A frequently used bond pad consists of an exposed aluminum pad. A gold bond wire can be bonded to this aluminum pad. This type of connection however is highly temperature dependent, posing potential reliability problems under operating conditions where the ambient temperature is known to be in excess of 150 degrees C. In addition, even when the ambient temperature is less than approximately 150 degrees C., the aluminum bond pad is susceptible to corrosion simply because it is exposed. Aluminum grows a passivating oxide layer in air and is as a consequence protected against corrosion. Aluminum wiring used in semiconductors, however, contains copper, which does not have a passivating oxide, and the Alxe2x80x94Cu alloy that is used is more vulnerable to corrosion. The corrosion of aluminum wires is caused by several sources such as chlorine transported through the plastic packaging and the passivation materials, chlorine from the etching compounds and as etching by-products, phosphorous acid formed from excess phosphorous in the phosphosilicate glass, etc. Only a small amount of chlorine is required to cause severe local corrosion of the aluminum lines. Aluminum corrosion can, in addition, occur very quickly after metal etching. A water rinse or a water vapor treatment is therefore typically applied to avoid etching introduced corrosion, whereby chlorine compounds and elemental chlorine must be removed from the metal surface immediately after plasma etching.
Materials that are typically used for bond pads include metallic materials, such as tungsten and aluminum, while heavily doped polysilicon can also be used for contacting material. The bond pad is formed on the top surface of the semiconductor device whereby the electrically conducting material is frequently embedded in an insulating layer of dielectric. In using polysilicon as the bond pad material, polysilicon can be doped with an n-type dopant for contacting N-regions while it can be doped with p-type dopant for contacting P-regions. This approach of doping avoids inter-diffusion of the dopants and dopant migration. It is clear that low contact resistance for the bond pad area is required while concerns of avoidance of moisture or chemical solvent absorption, thin film adhesion characteristics, delamination and cracking play an important part in the creation of bond pads.
The conventional processing sequence that is used to create an aluminum bond pad is shown in FIGS. 1 and 2.
The process starts with a semiconductor surface 10, FIG. 1, typically the surface of a silicon single crystalline substrate. A layer 13 of Intra Metal Dielectric (IMD) is deposited over the surface 10. A layer 17 of metal, typically aluminum, has been deposited over the surface of the layer 13 of IMD. Layer 17 of aluminum is patterned and etched typically using a layer of photoresist (not shown in FIG. 1) and conventional methods of photolithography and etching. After the bond pad 17, FIG. 2, has been created in this manner, a layer 11 of passivation is deposited over the layer 13 of IMD. An opening 15 that aligns with the bond pad 17 is created in the layer 11 of passivation, again using methods of photolithography and etching.
A conventional method that is used to create a solder bump over a contact pad is next highlighted. FIG. 3 shows an example of one of the methods that is used to create an interconnect bump. A semiconductor surface 10 has been provided with a metal contact pad 14, the semiconductor surface 10 is protected with a layer 12 of passivation. An opening 19 has been created in the layer 12 of passivation, the surface of the metal contact pad 14 is exposed through this opening 19. Next, FIG. 4, a dielectric layer 16 is deposited over the surface of the layer 12 of passivation. The layer 16 of dielectric is patterned and etched creating an opening 21 in the layer 16 of dielectric that aligns with the metal pad 14 and that partially exposes the surface of the metal pad 14. A layer 18 of metal, typically using Under-Bump-Metallurgy (UBM), is created over the layer 16 of dielectric, layer 18 of metal is in contact with the surface of the metal pad 14 inside opening 21. The region of layer 18 of metal that is above the metal pad 14 will, at a later point in the processing, form a pedestal over which the interconnect bump will be formed. This pedestal can be further extended in a vertical direction by the deposition and patterning of one or more additional layers that may contain a photoresist or a dielectric material, these additional layers are not shown in FIG. 4. These layers essentially have the shape of layer 16 and are removed during one of the final processing steps that is applied for the formation of the interconnect bump.
A layer of photoresist (not shown) is deposited, patterned and etched, creating an opening that aligns with the contact pad 14. A layer 20 of metal, such as copper or nickel, FIG. 5, that forms an integral part of the pedestal of the to be created interconnect bump, is next electroplated in the opening created in the layer of photoresist and on the surface of the layer 18 of metal, whereby the layer 18 serves as the lower electrode during the plating process. The final layer 22 of solder is electroplated on the surface of layer 20. The patterned layer of photoresist is then removed.
The layer 18 of metal is next etched, FIG. 6, leaving in place only the pedestal for the interconnect bump. During this etch process the deposited layers 20 and 22 serve as a mask. If, as indicated above, additional layers of dielectric or photoresist have been deposited for the further shaping of pedestal 18 in FIG. 4, these layers are also removed at this time.
A solder paste or flux is now applied to the layer 22 of solder, the solder 22 is melted in a reflow surface typically under a nitrogen atmosphere, creating the spherically shaped interconnect bump 22 that is shown in FIG. 6.
In addition to the above indicated additional layers of dielectric or photoresist that can be used to further shape the pedestal of the interconnect bump, many of the applications that are aimed at creating interconnect bumps make use of layers of metal that serve as barrier layers or that have other specific purposes, such as the improvement of adhesion of the various overlying layers or the prevention of diffusion of materials between adjacent layers. These layers collectively form layer 18 of FIG. 5 and have, as is clear from the above, an effect on the shape of the completed bump and are therefore frequently referred to as Ball Limiting Metal (BLM) layer. Frequently used BLM layers are successive and overlying layers of chrome, copper and gold, whereby the chrome is used to enhance adhesion with an underlying aluminum contact pad, the copper layer serves to prevent diffusion of solder materials into underlying layers while the gold layer serves to prevent oxidation of the surface of the copper layer. The BLM layer is represented by layer 18 of FIGS. 4 through 6. Contact pads, having dimensions of about 120xc3x97120 xcexcm, are in current practice frequently used as access or input/output contact points during wafer level testing of semiconductor devices. In view of the complexity and density of high performance semiconductor devices, these contact pads will, during a complete cycle of testing, be contacted a number of times. Testing is, as a matter of economic necessity, performed at high speed, which frequently results in landing the test probe on the surface of the contact pad at high speed, resulting in mechanical damage (in the form of probe marks) to the surface of the contact pad. Especially for memory products, a wafer is tested at least two times, that is before and after repair of faulty (weak or bad) memory lines. The distribution of the location of the probe mark over the surface of the contact pad is, in a well controlled testing production line, limited to an area of about 60xc3x9760 xcexcm. Surface damage to the contact pad may occur in the form of a dent in the surface of the contact pad or may even become severe enough that the surface of the contact pad is disrupted, resulting in the occurrence of burring in the surface of the contact pad. After the contact pads have in this manner been used as an I/O point for accessing the semiconductor device during high speed testing, a number of these contact pads are frequently used for the creation of solder bumps over the surface thereof. In instances where the surface of the contact pad is damaged, it is clear that the surface of the contact pad forms a poor basis on which to create a solder bump. The invention addresses this concern and provides a method whereby surface damage to contact pads is removed.
U.S. Pat. No. 6,162,652 (Dass et al.) provides for the testing of an integrated circuit device including depositing a solder bump on a surface of a bond pad.
U.S. Pat. No. 5,756,370 (Farnworth et al.) provides a compliant contact system for making temporary connection with a semiconductor die for testing and a method for fabricating the pliable contact system.
U.S. Pat. No. 5,554,940 (Hubacker) addresses the probing of semiconductor devices that have been provided with contact bumps and the formation of peripheral test pads.
A principle objective of the invention is to eliminate the effect of surface damage to I/O pads that has been caused by using these I/O pads as contact points for wafer level testing of semiconductor devices.
Another objective of the invention is to eliminate the effect of probe marks on the surface of I/O pads for I/O pads that have been used as contact points for wafer level testing of semiconductor devices.
In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. The area in the surface of I/O pads, which have been used for I/O pads during wafer level semiconductor device testing, is removed in the immediate vicinity of the surface area where the test probe contacts the I/O pad. This removal uses methods of metal dry etching or wet etching.